Variable length recording and coding system

  • Inventors: MIKAMI FUMIYUKI
  • Assignees: Canon Inc
  • Publication Date: December 11, 1991
  • Publication Number: JP-H03280268-A


PURPOSE: To increase a min. inter-bit spacing by specifying the value of a r at the time of conversion of the data of r bit to a code word of 2.r bits and specifying the line number of the 0 between 1 and 1 of a binary code word array connected with the code word after the conversion. CONSTITUTION: The 2 bits of the input data bit array are taken into a shift register 11 in a coding circuit and are latched by every one bit. Further, the 2 bits are sent by a latching circuit 12 to a code converting circuit 14. The input of the 2 bits and the input of the 1 bit from a state register 15 and total 3 bits are converted to the code words of the 2 bits in the circuit 14. The code words are outputted to a shift register 13 and the state 1 bit after transition is outputted to the state register 15. The serial-converted code words are sent to an NRZI modulating circuit by which the code words are subjected to NRZI modulation and are stored on a recording medium by a recording section. The coding circuit is easily constituted of a gate circuit according to this constitution. COPYRIGHT: (C)1991,JPO&Japio




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